checkpoint

23 files changed, 311 insertions, 9 deletions

diff --git a/src/build/sim86 b/src/build/sim86
index 49638e6..c04e9fe 100755
--- a/src/build/sim86
+++ b/src/build/sim86
diff --git a/src/code/sim86.cpp b/src/code/sim86.cpp
index b6fb57b..7903fb6 100644
--- a/src/code/sim86.cpp
+++ b/src/code/sim86.cpp
@@ -101,9 +101,9 @@ OperandsToValues(s32 *Registers,
     }
     else if(DestinationOperand->Type == Operand_Immediate)
     {
-        Assert(0 && "not implemented yet.");
+        Result.Destination = &DestinationOperand->Immediate.Value;
     }
-    else
+    else if(SourceOperand->Type != Operand_None)
     {
         Assert(0);
     }
@@ -121,7 +121,7 @@ OperandsToValues(s32 *Registers,
     {
         Assert(0 && "not implemented yet.");
     }
-    else
+    else if(SourceOperand->Type != Operand_None)
     {
         Assert(0);
     }
@@ -135,15 +135,16 @@ Run8086(psize DisassemblySize, u8 *Disassembly)
 {
     s32 Registers[Register_count] = {}; 
     u32 FlagsRegister = 0;
+    u32 IPRegister = 0;
     
-    u32 Offset = 0;
-    while(Offset < DisassemblySize)
+    while(IPRegister < DisassemblySize)
     {
         instruction Decoded;
-        Sim86_Decode8086Instruction(DisassemblySize - Offset, Disassembly + Offset, &Decoded);
+        Sim86_Decode8086Instruction(DisassemblySize - IPRegister, Disassembly + IPRegister, &Decoded);
         if(Decoded.Op)
         {
-            Offset += Decoded.Size;
+            u32 OldIPRegister = IPRegister;
+            IPRegister += Decoded.Size;
             
 #if SIM86_INTERNAL           
             printf("Size:%u Op:%s Flags:0x%x ;", Decoded.Size, Sim86_MnemonicFromOperationType(Decoded.Op), Decoded.Flags);
@@ -198,7 +199,6 @@ Run8086(psize DisassemblySize, u8 *Disassembly)
                 Assert(SourceOperand->Type == Operand_Register || SourceOperand->Type == Operand_Immediate);
                 
                 s32 Old = *Destination;
-                u32 OldFlags = FlagsRegister;
                 *Destination = (u16)((u16)(*Destination) - ((u16)(*Source)));
                 printf(" %s:0x%x->0x%x", 
                        Sim86_RegisterNameFromOperand(&DestinationOperand->Register),
@@ -220,11 +220,29 @@ Run8086(psize DisassemblySize, u8 *Disassembly)
                 
                 FlagsFromValue(&FlagsRegister, Decoded.Flags, *Destination);
             }
+            else if(Decoded.Op == Op_jne)
+            {
+                if(!(FlagsRegister & Flag_Zero))
+                {
+                    IPRegister += *Destination;
+                }
+            }
+            else if(Decoded.Op == Op_je)
+            {
+                if((FlagsRegister & Flag_Zero))
+                {
+                    IPRegister += *Destination;
+                }
+            }
             else
             {
                 Assert(0 && "Op not implemented yet.");
             }
             
+#if SIM86_INTERNAL
+            printf(" ip:0x%x->0x%x", OldIPRegister, IPRegister);
+#endif
+            
         }
         else
         {
@@ -256,9 +274,11 @@ Run8086(psize DisassemblySize, u8 *Disassembly)
                    Value, Value);
         }
     }
+    printf("     ip: 0x%04x (%d)\n", IPRegister, IPRegister);
+    
     char FlagsString[ArrayCount(FlagToCharMapping)] = {};
     FlagsToString(FlagsString, FlagsRegister);
-    printf("  flags: %s", FlagsString);
+    printf("  flags: %s\n", FlagsString);
 }
 
 void PrintUsage(char *ExePath)
diff --git a/src/data/listing_0046_add_sub_cmp b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp
index ba7e73d..ba7e73d 100644
--- a/src/data/listing_0046_add_sub_cmp
+++ b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp
diff --git a/src/data/listing_0046_add_sub_cmp.asm b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp.asm
index 287e958..287e958 100644
--- a/src/data/listing_0046_add_sub_cmp.asm
+++ b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp.asm
diff --git a/src/data/listing_0046_add_sub_cmp.txt b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp.txt
index 4b27dba..4b27dba 100644
--- a/src/data/listing_0046_add_sub_cmp.txt
+++ b/src/data/simulating_add_sub_cmp/listing_0046_add_sub_cmp.txt
diff --git a/src/data/listing_0047_challenge_flags b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags
index 58edaa0..58edaa0 100644
--- a/src/data/listing_0047_challenge_flags
+++ b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags
diff --git a/src/data/listing_0047_challenge_flags.asm b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags.asm
index 0a4cd1f..0a4cd1f 100644
--- a/src/data/listing_0047_challenge_flags.asm
+++ b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags.asm
diff --git a/src/data/listing_0047_challenge_flags.txt b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags.txt
index d33a1ca..d33a1ca 100644
--- a/src/data/listing_0047_challenge_flags.txt
+++ b/src/data/simulating_add_sub_cmp/listing_0047_challenge_flags.txt
diff --git a/src/data/simulating_conditional_jumps/listing_0048_ip_register b/src/data/simulating_conditional_jumps/listing_0048_ip_register
new file mode 100644
index 0000000..1aa90a5
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0048_ip_register
diff --git a/src/data/simulating_conditional_jumps/listing_0048_ip_register.asm b/src/data/simulating_conditional_jumps/listing_0048_ip_register.asm
new file mode 100644
index 0000000..f7fe1d7
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0048_ip_register.asm
@@ -0,0 +1,23 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 48
+; ========================================================================
+
+bits 16
+
+mov cx, 200
+mov bx, cx
+add cx, 1000
+mov bx, 2000
+sub cx, bx
diff --git a/src/data/simulating_conditional_jumps/listing_0048_ip_register.txt b/src/data/simulating_conditional_jumps/listing_0048_ip_register.txt
new file mode 100644
index 0000000..b5072f6
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0048_ip_register.txt
@@ -0,0 +1,13 @@
+--- test\listing_0048_ip_register execution ---
+mov cx, 200 ; cx:0x0->0xc8 ip:0x0->0x3 
+mov bx, cx ; bx:0x0->0xc8 ip:0x3->0x5 
+add cx, 1000 ; cx:0xc8->0x4b0 ip:0x5->0x9 flags:->A 
+mov bx, 2000 ; bx:0xc8->0x7d0 ip:0x9->0xc 
+sub cx, bx ; cx:0x4b0->0xfce0 ip:0xc->0xe flags:A->CS 
+
+Final registers:
+      bx: 0x07d0 (2000)
+      cx: 0xfce0 (64736)
+      ip: 0x000e (14)
+   flags: CS
+
diff --git a/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps
new file mode 100644
index 0000000..0a27d41
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps
diff --git a/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.asm b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.asm
new file mode 100644
index 0000000..f80bce6
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.asm
@@ -0,0 +1,24 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 49
+; ========================================================================
+
+bits 16
+
+mov cx, 3
+mov bx, 1000
+loop_start:
+add bx, 10
+sub cx, 1
+jnz loop_start
diff --git a/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.txt b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.txt
new file mode 100644
index 0000000..8005993
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0049_conditional_jumps.txt
@@ -0,0 +1,18 @@
+--- test\listing_0049_conditional_jumps execution ---
+mov cx, 3 ; cx:0x0->0x3 ip:0x0->0x3 
+mov bx, 1000 ; bx:0x0->0x3e8 ip:0x3->0x6 
+add bx, 10 ; bx:0x3e8->0x3f2 ip:0x6->0x9 flags:->A 
+sub cx, 1 ; cx:0x3->0x2 ip:0x9->0xc flags:A-> 
+jne $-6 ; ip:0xc->0x6 
+add bx, 10 ; bx:0x3f2->0x3fc ip:0x6->0x9 flags:->P 
+sub cx, 1 ; cx:0x2->0x1 ip:0x9->0xc flags:P-> 
+jne $-6 ; ip:0xc->0x6 
+add bx, 10 ; bx:0x3fc->0x406 ip:0x6->0x9 flags:->PA 
+sub cx, 1 ; cx:0x1->0x0 ip:0x9->0xc flags:PA->PZ 
+jne $-6 ; ip:0xc->0xe 
+
+Final registers:
+      bx: 0x0406 (1030)
+      ip: 0x000e (14)
+   flags: PZ
+
diff --git a/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps
new file mode 100644
index 0000000..7a95806
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps
diff --git a/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.asm b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.asm
new file mode 100644
index 0000000..8d2f484
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.asm
@@ -0,0 +1,38 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 50
+; ========================================================================
+
+bits 16
+
+mov ax, 10
+mov bx, 10
+mov cx, 10
+
+label_0:
+cmp bx, cx
+je label_1
+
+add ax, 1
+jp label_2
+
+label_1:
+sub bx, 5
+jb label_3
+
+label_2:
+sub cx, 2
+
+label_3:
+loopnz label_0
diff --git a/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.txt b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.txt
new file mode 100644
index 0000000..881a107
--- /dev/null
+++ b/src/data/simulating_conditional_jumps/listing_0050_challenge_jumps.txt
@@ -0,0 +1,38 @@
+--- test\listing_0050_challenge_jumps execution ---
+mov ax, 10 ; ax:0x0->0xa ip:0x0->0x3 
+mov bx, 10 ; bx:0x0->0xa ip:0x3->0x6 
+mov cx, 10 ; cx:0x0->0xa ip:0x6->0x9 
+cmp bx, cx ; ip:0x9->0xb flags:->PZ 
+je $+7 ; ip:0xb->0x12 
+sub bx, 5 ; bx:0xa->0x5 ip:0x12->0x15 flags:PZ->P 
+jb $+5 ; ip:0x15->0x17 
+sub cx, 2 ; cx:0xa->0x8 ip:0x17->0x1a flags:P-> 
+loopnz $-17 ; cx:0x8->0x7 ip:0x1a->0x9 
+cmp bx, cx ; ip:0x9->0xb flags:->CAS 
+je $+7 ; ip:0xb->0xd 
+add ax, 1 ; ax:0xa->0xb ip:0xd->0x10 flags:CAS-> 
+jp $+7 ; ip:0x10->0x12 
+sub bx, 5 ; bx:0x5->0x0 ip:0x12->0x15 flags:->PZ 
+jb $+5 ; ip:0x15->0x17 
+sub cx, 2 ; cx:0x7->0x5 ip:0x17->0x1a flags:PZ->P 
+loopnz $-17 ; cx:0x5->0x4 ip:0x1a->0x9 
+cmp bx, cx ; ip:0x9->0xb flags:P->CPAS 
+je $+7 ; ip:0xb->0xd 
+add ax, 1 ; ax:0xb->0xc ip:0xd->0x10 flags:CPAS->P 
+jp $+7 ; ip:0x10->0x17 
+sub cx, 2 ; cx:0x4->0x2 ip:0x17->0x1a flags:P-> 
+loopnz $-17 ; cx:0x2->0x1 ip:0x1a->0x9 
+cmp bx, cx ; ip:0x9->0xb flags:->CPAS 
+je $+7 ; ip:0xb->0xd 
+add ax, 1 ; ax:0xc->0xd ip:0xd->0x10 flags:CPAS-> 
+jp $+7 ; ip:0x10->0x12 
+sub bx, 5 ; bx:0x0->0xfffb ip:0x12->0x15 flags:->CAS 
+jb $+5 ; ip:0x15->0x1a 
+loopnz $-17 ; cx:0x1->0x0 ip:0x1a->0x1c 
+
+Final registers:
+      ax: 0x000d (13)
+      bx: 0xfffb (65531)
+      ip: 0x001c (28)
+   flags: CAS
+
diff --git a/src/data/simulating_memory/listing_0051_memory_mov b/src/data/simulating_memory/listing_0051_memory_mov
new file mode 100644
index 0000000..6907cff
--- /dev/null
+++ b/src/data/simulating_memory/listing_0051_memory_mov
diff --git a/src/data/simulating_memory/listing_0051_memory_mov.asm b/src/data/simulating_memory/listing_0051_memory_mov.asm
new file mode 100644
index 0000000..d27e348
--- /dev/null
+++ b/src/data/simulating_memory/listing_0051_memory_mov.asm
@@ -0,0 +1,30 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 51
+; ========================================================================
+
+bits 16
+
+mov word [1000], 1
+mov word [1002], 2
+mov word [1004], 3
+mov word [1006], 4
+
+mov bx, 1000
+mov word [bx + 4], 10
+
+mov bx, word [1000]
+mov cx, word [1002]
+mov dx, word [1004]
+mov bp, word [1006]
diff --git a/src/data/simulating_memory/listing_0051_memory_mov.txt b/src/data/simulating_memory/listing_0051_memory_mov.txt
new file mode 100644
index 0000000..e1ce4b0
--- /dev/null
+++ b/src/data/simulating_memory/listing_0051_memory_mov.txt
@@ -0,0 +1,19 @@
+--- test\listing_0051_memory_mov execution ---
+mov word [+1000], 1 ; ip:0x0->0x6 
+mov word [+1002], 2 ; ip:0x6->0xc 
+mov word [+1004], 3 ; ip:0xc->0x12 
+mov word [+1006], 4 ; ip:0x12->0x18 
+mov bx, 1000 ; bx:0x0->0x3e8 ip:0x18->0x1b 
+mov word [bx+4], 10 ; ip:0x1b->0x20 
+mov bx, [+1000] ; bx:0x3e8->0x1 ip:0x20->0x24 
+mov cx, [+1002] ; cx:0x0->0x2 ip:0x24->0x28 
+mov dx, [+1004] ; dx:0x0->0xa ip:0x28->0x2c 
+mov bp, [+1006] ; bp:0x0->0x4 ip:0x2c->0x30 
+
+Final registers:
+      bx: 0x0001 (1)
+      cx: 0x0002 (2)
+      dx: 0x000a (10)
+      bp: 0x0004 (4)
+      ip: 0x0030 (48)
+
diff --git a/src/data/simulating_memory/listing_0052_memory_add_loop b/src/data/simulating_memory/listing_0052_memory_add_loop
new file mode 100644
index 0000000..1f6d274
--- /dev/null
+++ b/src/data/simulating_memory/listing_0052_memory_add_loop
diff --git a/src/data/simulating_memory/listing_0052_memory_add_loop.asm b/src/data/simulating_memory/listing_0052_memory_add_loop.asm
new file mode 100644
index 0000000..189ed32
--- /dev/null
+++ b/src/data/simulating_memory/listing_0052_memory_add_loop.asm
@@ -0,0 +1,36 @@
+; ========================================================================
+;
+; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
+;
+; This software is provided 'as-is', without any express or implied
+; warranty. In no event will the authors be held liable for any damages
+; arising from the use of this software.
+;
+; Please see https://computerenhance.com for further information
+;
+; ========================================================================
+
+; ========================================================================
+; LISTING 52
+; ========================================================================
+
+bits 16
+
+mov dx, 6
+mov bp, 1000
+
+mov si, 0
+init_loop_start:
+	mov word [bp + si], si
+	add si, 2
+	cmp si, dx
+	jnz init_loop_start
+
+mov bx, 0
+mov si, 0
+add_loop_start:
+	mov cx, word [bp + si]
+	add bx, cx
+	add si, 2
+	cmp si, dx
+	jnz add_loop_start
diff --git a/src/data/simulating_memory/listing_0052_memory_add_loop.txt b/src/data/simulating_memory/listing_0052_memory_add_loop.txt
new file mode 100644
index 0000000..14da357
--- /dev/null
+++ b/src/data/simulating_memory/listing_0052_memory_add_loop.txt
@@ -0,0 +1,43 @@
+--- test\listing_0052_memory_add_loop execution ---
+mov dx, 6 ; dx:0x0->0x6 ip:0x0->0x3 
+mov bp, 1000 ; bp:0x0->0x3e8 ip:0x3->0x6 
+mov si, 0 ; ip:0x6->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x0->0x2 ip:0xb->0xe 
+cmp si, dx ; ip:0xe->0x10 flags:->CPAS 
+jne $-7 ; ip:0x10->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x2->0x4 ip:0xb->0xe flags:CPAS-> 
+cmp si, dx ; ip:0xe->0x10 flags:->CAS 
+jne $-7 ; ip:0x10->0x9 
+mov word [bp+si], si ; ip:0x9->0xb 
+add si, 2 ; si:0x4->0x6 ip:0xb->0xe flags:CAS->P 
+cmp si, dx ; ip:0xe->0x10 flags:P->PZ 
+jne $-7 ; ip:0x10->0x12 
+mov bx, 0 ; ip:0x12->0x15 
+mov si, 0 ; si:0x6->0x0 ip:0x15->0x18 
+mov cx, [bp+si] ; ip:0x18->0x1a 
+add bx, cx ; ip:0x1a->0x1c 
+add si, 2 ; si:0x0->0x2 ip:0x1c->0x1f flags:PZ-> 
+cmp si, dx ; ip:0x1f->0x21 flags:->CPAS 
+jne $-9 ; ip:0x21->0x18 
+mov cx, [bp+si] ; cx:0x0->0x2 ip:0x18->0x1a 
+add bx, cx ; bx:0x0->0x2 ip:0x1a->0x1c flags:CPAS-> 
+add si, 2 ; si:0x2->0x4 ip:0x1c->0x1f 
+cmp si, dx ; ip:0x1f->0x21 flags:->CAS 
+jne $-9 ; ip:0x21->0x18 
+mov cx, [bp+si] ; cx:0x2->0x4 ip:0x18->0x1a 
+add bx, cx ; bx:0x2->0x6 ip:0x1a->0x1c flags:CAS->P 
+add si, 2 ; si:0x4->0x6 ip:0x1c->0x1f 
+cmp si, dx ; ip:0x1f->0x21 flags:P->PZ 
+jne $-9 ; ip:0x21->0x23 
+
+Final registers:
+      bx: 0x0006 (6)
+      cx: 0x0004 (4)
+      dx: 0x0006 (6)
+      bp: 0x03e8 (1000)
+      si: 0x0006 (6)
+      ip: 0x0023 (35)
+   flags: PZ
+